Senior Engineer II – Verification
Full Time
Chennai
Posted 7 months ago
Job Features
| Job Category | IT |
| Experience | 7 - 10 yrs |
| Skills | System verilog, UVM, test bench |
| Primary skills | System verilog, UVM, test bench |
| Education | B.E / B.Tech |
| Openings | 1 |
| Job Description | ● To play the role of Verification engineer at the Block level verification. ● Develop verification test plans from design specifications. ● Development of test environments using System Verilog and UVM verification methodologies. ● Integration with RTL and basic simulation bring-up for the design. ● Create multiple test cases as per test plan and launch regressions. ● Generate Code/Functional coverage, analyze coverage results and correlate with the test plan. ● Working the design team members to identify and quickly resolve problems with the design. ● Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenge Requirements/Qualifications: ● Domain Expertise : AHB, AXI, PCIe, USB and Ethernet. ● Languages (must): Verilog, system Verilog ● Methodologies (One of them is must): OVM/UVM/VMM ● EDA Tools (One of them is must): Questasim, VCS, NCSim, NCVerilog ● Experience in developing Test Bench components in both block level and SOC level. ● Experience in Creating test plan and Writing test sequence. ● Functional Coverage, Code Coverage & Assertions (OVA, SVA, PSL) (Desirable) ● Good analytical and problem-solving skills ● Excellent written and verbal communication in English. ● Good teamwork and the desire to excel in a competitive environment. Qualification: ● Bachelor's Level Degree (ECE, EE, CSE, IT / preferred specialization) with more than 7 years of work experience |