REQUIREMENTS/QUALIFICATIONS:

• Good Knowledge on physical aware synthesis, advance synthesis for power and area optimization, Vector synthesis.
Good Understand Design-For-Test concepts and methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage,
and generation).
•
• Develop Constraints, analysis and debugging for Func, BIST and DFT modes
Full chip and block level timing closure for various stages of the entire design process (RTL, Synthesis, Place and Route
and STA Signoff).
• Enhance and maintain all STA flows and methodology for multiple designs and across different technologies.
• Work on all aspects of timing closure including Design rule checks, constraint validation, Noise analysis etc.
• Work with various IP owners in developing and refining STA constraints for both full chip and block level.
• Low power flow/CPF and conformal low power debug.
• Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure
• Good in low power techniques and Conformal Low Power
• Developing CPF/UPF files
• Running Logical Equivalence Check and resolving the issues
• Scripting skills in any programming language (preferably Perl, TCL and Shell)
• Ability in debugging, problem solving and analytical skills.
• Good communication skills
Experience:
• Bachelors/Masters in Electronics or equivalent degree with 9+ years of experience